1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a non-volatile semiconductor memory device and a reading method of the non-volatile semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices are generally divided into two groups: volatile memory devices, including Dynamic Random Access Memory (DRAM) devices and Synchronous Random Access Memory (SRAM) devices; and non-volatile memory devices, including Electrically Erasable Programmable Read Only Memory (EEPROM) devices, Ferroelectric Random Access Memory (FRAM) devices, Phase-change Random Access Memory (PRAM) devices, Magnetic Random Access Memory (MRAM) devices, and flash memory devices. Whereas the volatile memory devices lose the data stored therein when power supply is cut off, the non-volatile memory devices retain the data stored therein even though power supply is cut off. Particularly, since flash memory devices have such advantages as high programming speed, low power consumption, and large-capacity data storage, they are widely used as storage media for computer systems.
Flash memory devices are generally divided into NAND-type flash memory devices and NOR-type flash memory devices. Since the NOR-type flash memory devices have a structure where each memory cell is independently coupled with a bit line and a word line, the NOR-type flash memory devices have excellent random access time characteristics. On the other hand, the NAND-type flash memory devices include a plurality of memory cells coupled in series. Only one contact is required for each cell string. Therefore, the NAND-type flash memory devices may have a high integration degree. For this reason, usually the NAND-type flash memory devices are used as high-integration non-volatile memory devices.
FIG. 1 is a schematic view illustrating a conventional NAND-type flash memory device.
Referring to FIG. 1, the conventional NAND-type flash memory device 10 includes a memory cell array 12 and an input/output control circuit 14. The memory cell array 12 programs data that are transferred through bit lines EVEN_BL and ODD_BL, or provides programmed data through the bit lines EVEN_BL and ODD_BL. The input/output control circuit 14 transfers external data to be programmed through the bit lines EVEN_BL and ODD_BL, or outputs data received from the bit lines EVEN_BL and ODD_BL to the outside of the NAND-type flash memory device 10.
The memory cell array 12 includes a first cell string ST1 and a second cell string ST2. Each of the first cell string ST1 and the second cell string ST2 has its one end coupled with a bit line, EVEN_BL or ODD_BL, and the other end coupled with a common source line CSL. For the illustrative purpose, it is assumed that the memory cell array 12 includes two cell strings, which are the first cell string ST1 and the second cell string ST2, and the bit lines EVEN_BL and ODD_BL respectively coupled with the first cell string ST1 and the second cell string ST2 are referred to as a first bit lines EVEN_BL and a second bit lines ODD_BL. A first switch SW1 and a second switch SW2 are disposed on both ends of each of the first cell string ST1 and the second cell string ST2 A plurality of memory cells MC0 to MCM are serially coupled with each other between the first switch SW1 and the second switch SW2. The first switch SW1 is coupled with a drain selection line DSL. The first switch SW1 selectively connects, or disconnects, a memory cell MCM to, or from, the bit line EVEN_BL or ODD_BL, according to the voltage level of the drain selection line DSL. The second switch SW2 is coupled with a source selection line SSL. The second switch SW2 selectively connects, or disconnects, a memory cell MC0 to, or from, the common source line CSL, according to the voltage level of the source selection line SSL. Also, the memory cells MC0 to MCM are coupled with a plurality of word lines WL0 to WLM in one-on-one. Data are programmed or read according to the voltage level that is applied to the word lines WL0 to WLM.
Meanwhile, the input/output control circuit 14 includes a page buffer (not shown) and an input/output circuit (not shown). The page buffer latches a data to be programmed or a data to be read. The input/output circuit serves as an interface between the page buffer and the outside. The technologies of the page buffer and the input/output circuit are well known and used, so detailed description about the page buffer and the input/output circuit is not provided herein.
The NAND-type flash memory device 10 having the above-described structure may have an excellent integration degree. The NAND-type flash memory device 10, however, has the following drawbacks, which are described hereafter with reference to FIGS. 2A to 2D.
FIGS. 2A and 2B illustrate memory cells to describe the concern originating from retention characteristics at a high temperature, whereas FIGS. 2C and 2D illustrate memory cells to describe the concern originating from read disturbance.
Referring to FIG. 2A, when memory cells MCX−1 and MCX+1 that are adjacent to a memory cell MCX programmed with a data is in an erase state, mobile ions included in electrical charges move to the surrounding area of the programmed memory cell MCX due to a field between floating gates. As a result, the threshold voltage VT of the programmed memory cell MCX is changed, for example, dropped. Retention characteristics are deteriorated. On the other hand, as illustrated in FIG. 2B, when the memory cells MCX−1 and MCX+1 that are adjacent to the programmed memory cell MCX is in a program state, the mobile ions in the surrounding region do not move, deteriorating the retention characteristics.
Subsequently, the drawback originating from read disturbance is described with reference to FIG. 2C. During a read operation, a read voltage SEL_BIAS, which is lower than a read pass voltage VREAD to be described later, is applied to a word line WLX coupled with the selected memory cell MCX, while the read pass voltage VREAD, which is higher than the threshold voltage VT of the memory cells MCX−1 and MCX+1, is applied to word lines WLX−1, WLX+1, and WLX+2 coupled with the unselected memory cells MCX−1 and MCX+1. Herein, when the memory cells MCX−1 and MCX+1 that are adjacent to the programmed memory cell MCX is in an erase state, the read pass voltage VREAD and the potential of the erase-state memory cells MCX−1 and MCX+1 are added up and the lateral field works on the selected memory cell MCX. As a result, there may be a concern in that a charge loss phenomenon may occur in the selected memory cell MCX due to the lateral field. On the other hand, as illustrated in FIG. 2D, when the memory cells MCX−1 and MCX+1 that are adjacent to the selected memory cell MCX is in a program state, the lateral field decreases because the programmed memory cells MCX−1 and MCX+1 have negative potential and then the lateral field by the read pass voltage VREAD attenuates.
Meanwhile, the above concerns become more serious in case of a memory cell block programmed with a system firmware data. A system firmware data is not information used by a memory but information used by a controller to operate the memory. Since the system firmware data is continuously read out whenever the memory operates after the memory is programmed once, the above-mentioned concerns may appear more distinctively when the memory cell block is a memory cell block programmed with the system firmware data.